Pseudo-interrupt and pseudo-interrupt handling of LPC2292

Pseudo-interrupt and pseudo-interrupt handling of LPC2292

Industrial Ethernet has better performance than the field bus, and is in the process of continuous development and improvement, so the development of industrial Ethernet-based equipment has good market prospects. The embedded controller designed in this paper uses the microcontroller LPC2292 based on ARM7TDMIS [12]. The bottom layer of the controller is connected to the field bus CAN and upward to the Ethernet / IP industrial Ethernet. In order to improve reliability, redundant control technology is applied and an identical redundant controller is prepared. Through the LVDS interface, the controller is connected to the redundant controller and monitors each other online. At the same time, this article uses an embedded real-time operating system μC / OS-II [3].

The embedded controller adopts high-performance 32-bit single-chip microcomputer LPC2292. However, LPC2292 has the possibility of generating a pseudo interrupt during normal operation. If it is not handled correctly, it may have serious consequences. This article has made a comprehensive analysis of this, and handled it flexibly according to different situations; finally, the problem of pseudo-interruption was completely solved, and the hidden dangers in the embedded controller were eliminated.

The resources of LPC2292 used in this article are watchdog, timer TIMIER0, UART0, UART1, CAN1, and are connected to the Ethernet controller chip RTL8019AS through an external bus. Set the received data Rx of CAN1 as a fast interrupt, it is the only fast interrupt. UART1 is connected to the LVDS chip, and UART0 communicates with external devices through the RS232 conversion chip.

1 Causes of pseudo interrupts

Due to asynchronous interrupt handling, pseudo interrupts may appear in the LPC2292 microcontroller based on ARM7TDMIS. If it is not handled correctly, it may cause serious consequences. The asynchronous nature of interrupt handling comes from the interaction between the core and the vectored interrupt controller (VIC). If an interrupt is detected in the kernel and the state of the VIC changes during the kernel actually starts to process the interrupt, the asynchronous nature of the interrupt is generated [4].

The application may go through the following steps:

â‘  VIC judges whether there is IRQ interrupt. If so, send IRQ signal to the core.
â‘¡ The kernel saves the IRQ state.
â‘¢ Execute multiple cycles of pipeline processing.
â‘£ The kernel loads the IRQ address from the VIC.

If the state of the vectored interrupt controller changes when step â‘¢ is executed, a pseudo interrupt will occur. Therefore, a pseudo interrupt will occur in the following two cases.

â—† In step â‘¢, the off interrupt instruction was executed.
â—† The interrupt flag of the interrupt sending IRQ signal to the vector interrupt controller is lost. This may happen when the RDA / CTI interrupt of UART0 / UART1 is enabled [5].

When entering a pseudo interrupt, VIC cannot clearly identify the interrupt that generated the interrupt request, and finally can only return to the default interrupt of VicDefVectAddr (0xFFFFF034) for processing. Therefore, if the pseudo interrupt is not handled correctly, it may lead to serious consequences.

2 Processing of pseudo interrupts

In this controller, the place where the pseudo interrupt may occur is: off interrupt, feed watchdog, UART0 communication and UART1 communication. The design idea of ​​this article is: try to avoid generating false interrupts; if it can't be avoided, write the corresponding processing procedures.

2.1 Handling of interrupt instructions

The shutdown interrupt instruction OS_ENTER_CRITICAL () in μC / OS-II does not use the direct shutdown interrupt, but first enters the management mode, sets the register SPSR, and turns off the IRQ interrupt when exiting. This eliminates the possibility of spurious interruptions caused by off-interruptions.

2.2 Handling of watchdog

When feeding the watchdog, IRQ and FIQ must be turned off first, otherwise unexpected reset may occur, causing the controller to not work. The first thing in the periodic clock beat interrupt program is to feed the watchdog. If IRQ is turned off when entering the clock tick interrupt, the occurrence of a pseudo interrupt can be avoided. Of course, FIQ must be turned off before feeding the dog, and then FIQ must be turned on after feeding the dog. Turning off FIQ will not cause a pseudo interrupt [1].

2.3 Processing of UART0 and UART1

In UART0 (the same is true for UART1), when the UART0 Rx FIFO reaches the trigger point defined in the register U0FCR7: 6 (for example, receiving 4 characters), an RDA interrupt occurs. When the depth of UART0 Rx FIFO is lower than the trigger point, the RDA interrupt flag is cleared.

When the UART0 Rx FIFO contains at least 1 character, and there is no UART0 Rx FIFO action within the time of receiving 3.5 ~ 4.5 characters, the CTI interrupt is generated. Any action of UART0 Rx FIFO (read or write UART0 RSR) will clear the CTI interrupt flag.

The CTI pseudo interrupt occurs as follows: For example, the UART0 Rx FIFO has received 2 characters and the time exceeds 3.5 ~ 4.5 characters, the CTI interrupt occurs; but then there are characters coming in, so the CTI interrupt flag is cleared. The vectored interrupt controller cannot recognize who generated the interrupt, and a pseudo interrupt occurs.

The RDA pseudo-interrupt occurs as follows: Take the reception of 4 characters for the RDA interrupt as an example. For example, the UART0 Rx FIFO has received 3 characters and the CTI interrupt occurs when the time exceeds 3.5 ~ 4.5 characters. When the system correctly handles the CTI interrupt, exactly one character comes in, so that the number of characters in the UART0 Rx FIFO is exactly 4, so the RDA interrupt occurs. But because the CTI interrupt is processed first, the CTI interrupt program first reads the characters in it, so that the number of characters in the UART0 Rx FIFO is less than 4, so the RDA interrupt flag is cleared. When the system handles the RDA interrupt, a pseudo interrupt occurs.

It can be seen that the existence of the CTI interrupt is the culprit of generating pseudo interrupts for UART0 and UART1. UART1 is connected to the LVDS interface for online monitoring of the controller and redundant controller. The method of sending only one character at a time makes the CTI interrupt impossible, thus completely eliminating the possibility of UART1 generating a pseudo interrupt.

The controller only has the possibility of generating a pseudo interrupt in the UART0 interrupt. When a pseudo interrupt occurs, the system copies the address in the default interrupt address register VICDefVectAddr to the vector address register VICVectAddr, and the system executes the program at that address. Therefore, it is necessary to write the corresponding pseudo interrupt processing program, and put its first address into VICDefVectAddr. In the process of handling pseudo interrupts, the characters in the UART0 Rx FIFO should be read out as soon as possible to avoid loss.

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