FPGA-based AC motor driver current controller 3

Simulation and algorithm improvement steps
As mentioned earlier, the simulation steps have been demonstrated in the Matlab-simulink software environment. Its objectives are: to change the functionality of the complete control system; to find the appropriate sampling period and fixed-point format improvements for each control variable, as required by the control system's defects. With the use of simulated continuous time modules, the development of functional modules can cause these functions to change successfully. However, the parameterization of each combined digital algorithm is obtained under the influence of the study of the sampling period and the fixed-point format. With this in mind, the choice of each fixed-point format is derived from an adaptable method [30], [31]. At this level, simulation is implemented in the development of a digital fixed-point model using the system-generated toolbox [32]. However, for each proposed second level module, the concept of data flow graph (DFG) is proposed. DFG is a graphical representation of an algorithm that includes an untimed specification consisting of points and edges. Each point represents a simple algorithmic operation, or a simple mathematical or logical function, with each edge corresponding to a data conversion. For example, as shown in Figure 4(a), the DFG graph of the second algorithm level shows the following functions: (1) As shown in the association graph DFG, two applications can be completed in the parallel mode, but the additional applications depend on The results of both applications have been achieved and can only be achieved if the results of both applications are achieved. Therefore, the DFG graph clearly represents the data parallelism and the potential parallelism of the algorithm. Figure 3 shows the different steps presented. It is worth noting that, so far, the choice of target devices has not been available, because module separation and fixed-point improvement are also applicable to DSP controllers [33].
Fig.3.Development of DFGs.
Step optimization
The step optimization is based on the A3 technology [28]. The purpose of this method is to achieve the hardware structure optimization of the given algorithm under the space and time constraints if the FPGA-based design is performed. In each DFG diagram, some operations are used several times. If some operations use n times, then A3 will perform factorization but still apply to this operation, except that it only uses m times, and m Modular hardware structure design
For each module in the library, you need to define a data channel and a control device. The data channel in the structure can be used to replace the data bus between the operator corresponding to the node in the final graph and the operator corresponding to the edge. The data bus conversion is controlled by the control device, which may simply be referred to as a finite state machine (FSM). The structures of Figures 5(a) and 5(b) correspond to DFG and FDFG in Figure 4, respectively. It is worth noting that the data channel that has been obtained is actually a pseudo-copy of the corresponding graphic. In addition, the structure of the factorization is much larger than the structure of the structure that cannot be decomposed.
Each of the developed modules in the library features input and output formats, reusability, potential, and communication protocols. All of these features must be clearly indicated in the corresponding data table to facilitate development and utilization. Figure 6 shows the general structure of a reusable module in a second level module. The data channel consists of basic operators such as adders, multipliers, multiplexers, registers, and so on. The data conversion between these basic operators is done by a controller that is synchronized by the clock signal (Clk). The control unit of each module is activated by a "Start" pulse signal. When the process of calculating the time is over, an "End" pulse signal indicates to the global control that the module's data output channel can continue to be used.
Fig. 6. (a) Generic module architecture. (b) TIming diagram of the module. As for the development of the hardware structure of the third-level module, it can be said that it uses the blocks in the first and second-level modules in the library to operate. of. Therefore, the data channel is an instantiation of the combination of the first and second level modules, which is connected to the data bus. To this extent, the structure of the second level module can be considered a coarse grain operator. For this type of operator, an A3 factorization process can only be applied once. So, if the control algorithm includes two PI controllers, then the design can only arbitrarily choose the PI controller with the only one factorization. The second level of modules is easy to operate and control, depending only on their Start and End signals. The coordination of these modules is accomplished by the global control device signaling the local control device at a clearly defined point in time, as shown in Figure 7. The global control unit is of course also activated by the "Start" pulse signal and then ended in the "End" pulse signal generated after the output data has been completed. For this configuration, the third level module also operates in the same level of module structure in the same manner. However, the structure of each level module can be encoded by the structural method VHDL language.
Verify the design structure
The first step in verification is to use the Modelsim and Maltab software tools together for process operation simulation. This step allows the benign functions in the design structure to be modified by writing VHDL, and can be tested through a series of experimental platform input waveforms. The second verification step is performed at the system level by hardware in the loop operation step. The purpose of this process is to ensure the first experimental guarantee, which is completed in real time by hardware in the test structure, as shown in FIG. It mainly consists of three modules. The first is to generate the promotion mode and save it in the FPGA memory module. These facilitation models are directly derived from the simulation phase and can be further compared to the simulation system. The second module is the structure that is used for testing, and the third module is a communication interface module that connects the FPGA to the PC host. The computational output of this structure should be tested centrally and sent to the host PC via the communication interface for comparison with the results of the simulation in the Matlab environment. Once this test result is verified successfully, the structure of the secondary design will be applied to the actual.
Fig. 8. Hardware-in-the-loop procedure. [30] D. Menard and O. SenTIeys, "AutomaTIc evalua TIon of the accuracy of fixed-point algorithms," in Proc. IEEE/ACM Conf. Des., Autom. And Test Eur., 2002, pp. 529â€“535, CD-ROM. [31] F. Zhengwei, JE Carletta, and RJVeillette, â€œA methodology for FPGA-based control implementation,â€ IEEE Trans. Control Syst. Technol., vol .13, no. 6, pp. 977â€“987, Nov. 2005. [32] Xilinx, Data Book, 2006. [Online]. Available: [33] Texas Instruments DSC Group, A Software Modularity Strategy for Digital Control System Motor .SPRU485A, Aug. 2001, revised Oct. 2003.
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