Synchronous display design of VGA video and LED display

The display screen is divided into two kinds of synchronous and asynchronous from the communication control mode. The synchronous control mode is real-time communication between the host computer and the screen body. The asynchronous control mode is that the host computer and the screen operate independently, but the host computer needs to edit and send the display information to the display body. This article presents the design of information display based on the synchronous display of the host computer.

1. Overall system design

The system hardware is divided into three parts. First, the VGA monochrome digital video signal, pixel clock, line synchronization, and frame synchronization are extracted from the graphics card in real time through the graphics card real-time extraction circuit. After processing, they are transmitted by the output medium; the second part is the CRT video signal to the LED display Signal conversion circuit, which selects, stores, reads, and distributes the image signal transmitted from the transmission medium into a display signal corresponding to the LED dot matrix screen; the third part is the LED driver board, which receives the converted signal The LED displays signals and assigns to the pixels corresponding to the LED dot matrix screen to drive the LED display.

Second, the graphics card display information real-time extraction circuit

In the VGA mode, when a certain color is displayed on the VGA, the video memory first outputs a color number, which is actually used to select the palette register, and the selected palette register is generated again. An eight-bit index address is used to select the digital-to-analog converter (DAC color register). There are 256 DAC color registers. Each register consists of 18 bits. When a color register is selected, the 18-bit digital signal Carry out analog-to-digital conversion and convert it into analog red, green, and blue signals, and send it to an analog monitor to scan the graphics card.

When VGA works in display mode 18, that is, in sixteen-color mode, the lower four bits (from P0 to P3) of the eight-bit index address output by the palette register are actually digital video signals blue, green, red, and brightness Signal, we can use this feature of VGA to directly extract monochrome digital video signals. In the actual circuit, this function is realized through the 26-core feature socket of the graphics card. Among them, P0 to P7 are eight-bit index addresses, and pins 17, 21, and 23 are pixel clock, line synchronization, and field synchronization, respectively. On the one hand, the feature socket sends these signals to the color register anti-analog monitor, and on the other hand, it can be externally output. Therefore, we directly extract a single-channel video signal from the 26-core feature socket of the graphics card, after eight-bit serial conversion and conversion Transmitted through the long line, at the same time extract the pixel clock, field synchronization signal, line synchronization signal, for subsequent signal conversion and display. Eight-bit serial / parallel conversion is based on two reasons: one is that in the VGA graphics mode, one pixel is composed of eight bits, and the eight-bit parallel output realizes the transmission of one pixel and one pixel; the second is eight-bit serial / parallel conversion The data transmission rate is reduced, which facilitates long-term transmission.

The VGA scanning timing is different from the LED screen scanning timing. Therefore, the VGA video signal must be converted into a display signal corresponding to the LED large screen. This is mainly achieved by pairing two SRAMs.

(SRAM1 and SRAM2) read and write to complete. The two SRAMs are alternately in the read and write state. Suppose that in a certain field, SRAM1 is in the write state and SRAM2 is in the read state. At this time, the write signal of SRAM1 is valid and the read signal is invalid. At the same time, the write address generated by the write address generator is Strobe input SRAM1, so that the digital video signal is written to SRAM1; for SRAM2, the write signal is invalid, the read signal is valid, and at the same time, the strobe read address input SRAM2, so as to read the data written in the previous field in SRAM2, use For distribution, transmission and display.

(1) Selection of VGA video signal

The resolution of the VGA video is different from the LED large screen. In this system, the resolution of the large LED screen we realized is 256 × 128, and when the VGA works in the 18 mode, the resolution is 640 × 480. In this way, the LED screen The entire video image cannot be displayed completely, but only a part of it can be selected for synchronous display. The selection of VGA video images is done by writing the address generator and reading the address generator. The write address generator generates a write control signal while generating the write address. The control signal is valid during the selected row in a frame, and is invalid for the rest of the time, so that only the data of the selected row is written into the SRAM. The selection is the same; the read address generator generates a read control signal while generating the read address, which controls the read shift signal to be valid only during the selected column, that is, only the data of the selected column is shifted out, thereby completing The selection of VGA video signal column.

(2) SRAM data reading and distribution

The data stored in the SRAM needs to be read out and allocated in a certain order to make it correspond to the LED large screen. Here, we use a partition circuit method, that is, the entire LED large screen is divided by a multiple of 16, the LED large screen has a total of 256 OK, so it is divided into sixteen partitions. Data is read out and allocated in the following order: first, the first pixel in the first row of the first partition, then the first pixel in the first row of the second partition, ... the first pixel in the first row of the sixteenth partition , Next is the second pixel in the first row of the first partition ... In this order, the read data goes through the eight-bit shift register and is serially output, so that the data at the corresponding positions of the sixteen partitions are transmitted at the same time.

The use of partition circuits has two advantages: first, after the LED large screen is divided into sixteen partitions, the data transmission rate is reduced to one-sixteenth of the original, which is convenient for data transmission; second, the LED afterglow time is short, The screen refresh frequency is required to be high. If the frequency is refreshed, it will take a long time and flicker will occur. After using the partition circuit, sixteen partitions are refreshed at the same time. In this way, the screen flicker is overcome without increasing the complexity of the hardware phenomenon.

Third, the drive circuit

The data output by the conversion circuit enters the LED driver circuit board, and the image data must be accurately transmitted and distributed to the corresponding LED dot matrix pixels. The system uses dynamic progressive scanning to drive the LED display. Because the data of each partition is transmitted at the same time, the data transmission distribution and LED drive of each partition are consistent. In this system, the LED modules used are 8 × 8dot row common anode and column common cathode modules. The row common anode drive mode is adopted, that is, the image data is input to the cathode, and the LED display is driven by applying a high level to the common anode. The input of the image data is through the eight-bit shift register 595, each 595 chip corresponds to an LED module. At the beginning of a field, first, the shift signal controls the first line of data input. Latch signal, data latch output to the LED module, at the same time, the first row of common anode input a high level, lighting the first row; during the lighting of the first row, at the same time shift input the second row of data, the second After all rows are shifted in, another latch pulse appears, and the common anode high level of the first row disappears, and the common anode input high level of the second row drives the display of the second row, and the first row goes out ... While lighting the previous line, shift in the second line of data to keep the screen continuous.

By the above three parts of hardware, the synchronous display of VGA video and LED display screen is realized, so that the LED large screen tracks the VGA video display.

4. Conclusion

The information display of this system is not affected by the environment, and it can achieve high-brightness display. The system can select the screen size according to the information display requirements, thereby controlling the cost, and it is very practical. It has been applied in the automobile comprehensive performance detection system. Although this article studies monochromatic systems, this method can also be extended to full-color display systems.

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