The H.264 standard can produce high-quality pictures at a low bit rate, mainly using adaptive loop filtering. H.264 adopts block-based motion compensation. Block-based motion compensation can reduce the code rate very well, but it also causes the square effect. Therefore, H.264 adopts an adaptive filtering algorithm, which can reduce the square effect very well, but at the same time it also brings great computational complexity. In H.264, the filtered data will be used as the reference frame for the next frame, so it is also called loop filtering. Research shows that in the H.264 decoding process, motion compensation (MC) accounts for about 30%, and loop filtering (DF) accounts for about 20% of the decoding time. Therefore, a good design of MC and DF is crucial to the performance of the decoder. important. 1 Data used in the filtering process In H.264, in the case of MBAFF, the macroblocks all appear in the form of macroblock pairs. Therefore, when storing data, it is also considered to store data in units of one macroblock pair. In a macroblock pair, the data to be manipulated during the entire process during filtering is shown in Figure 1. Each small square represents a 4 & TImes; 4 pixel block. The data pointed to by up is needed to filter the mb_up macroblock. This design supports MBAFF. In the filtering process, frame and field conversion are needed, so it is necessary to use Go to the block on the second line above. When filtering the leftmost block, you need to use the column of data indicated by left in the figure. Figure 1 Data in filtering 2 DRAM planning and design DRAM is a low-cost, large-capacity, widely used storage medium, and it operates very quickly on large-scale data. However, due to the concept of Row in DRAM. In the case of operating different Rows, the DRAM must first close the current Row and activate the required Rows at the same time, which causes a lot of overhead. Imagine reading 10 data in the same Row and 10 data in 10 Rows respectively. The time cost of the latter will be 5-6 times that of the former. Therefore, DRAM is not suitable for random and scattered data access. Due to the existence of Row, the design of the data structure in DRAM is particularly important. To minimize the access between different Row, so as to improve the efficiency of data access. In this design, a 64-bit DRAM is used, which can store 8 pixel values. The brightness Y and chroma UV of an image are stored in a continuous space. The final image after H.264 decoding is stored in the DRAM. The display module continuously takes data from the DRAM and sends it to the display. The motion compensation unit also takes the reference frame data from the DRAM. Therefore, the bandwidth of DRAM is particularly tight. Reasonable allocation of DRAM bandwidth is an important aspect to be considered in the design. Because many modules require DRAM operation, in order to effectively manage DRAM, DRAMCONtrol module is set to control DRAM. 3 Design of DRAMControl module The DRAMControl module controls the interaction between DRAM and other external modules, and is the interface between DRAM and other external modules. The main functions include the automatic refresh of DRAM and the generation of DRAM commands. Because there are many states when DRAM works, the state machine is adopted in this design. The state diagram is shown in Figure 2. Figure 2 State transition diagram in DRAMControl In the design, a uniform refreshing method is adopted. Every certain time, the refresh is completed after the process of “IDLE → PRECHALL → AUTORF → IDLEâ€. The main body of the state transition is the process of reading and writing operations. The decision state (Decision) takes one clock cycle to determine whether the Row to be executed by the current operation is in the activated state. Row (completed through PRECH and ACT status); if it is activated, read and write operations directly. For the write operation, the three states of WRITEUP or WRITELEFT and WRITE are designed to be written to DRAM for the data of the upper macroblock, the left macroblock and its own macroblock to be updated after the filtering in H.264 is completed. The seamless connection in time constitutes a complete and consistent BurST write operation; if the data of the upper macroblock or the data block of the left macroblock is in a different row from the data block of the macroblock to be filtered, it is in the WRITEUP or WRITELEF state Realize the write operation of the data block that is not in this TIle. The write efficiency in this case is obviously lower than when it is in the same Row, but this is inevitable when the macro block is at the leftmost or topmost side of the Row The upper macroblock data or the left macroblock data block must belong to other Rows. In this design, one address of the DRAM is stored in the same row as the next block, so this avoids cross-Row operations at most. For write operations in other cases, use the WRITE state to complete.
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