Electronic enthusiasts : Verilog can use the preprocessor command `include "filename" to include new files. The location of the `include "filename" needs to be after the module declaration. Here is an example for everyone to understand, param.h stores the parameter LENTH, and the top mult.v uses it. Mult.v code is as follows 1 module mult ( 2 input clk, 3 input rst, 4 input [LENTH-1:0] A, 5 input [LENTH-1:0] B, 6 output [LENTH-1:0] C 7); 8 9 `include "param.h" 10 11 reg [LENTH-1:0] c_reg; 12 13 always@(posedge clk or negedge rst) 14 if(rst == 1'b0)begin 15 c_reg <= 32'b0; 16 end 17 else begin 18 c_reg <= A*B; 19 end 20 21 assign C = c_reg; twenty two 23 endmodule24 Param.h code is as follows 1 parameter LENTH = 32; Integrated RTL diagram
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