A single-phase VFD, also known as a variable frequency drive, is a specialized electronic device used for precise control and regulation of single-phase motors. Unlike three-phase motors that are commonly used in industrial applications, single-phase motors are predominantly found in residential and small-scale applications.
The primary function of a single-phase VFD is to control the frequency and voltage supplied to the single-phase motor, thereby enabling accurate regulation of motor speed. By adjusting the frequency and voltage output, the VFD allows for smooth and precise control over the motor's rotational speed. This feature is particularly useful in applications where speed control is required, such as in residential HVAC systems, small-scale machinery, and household appliances.
Energy efficiency is a significant advantage offered by single-phase VFDs. By adjusting the motor speed to match the load requirements, the VFD reduces energy wastage and improves overall energy efficiency. When the motor operates at a lower speed during periods of low demand, energy consumption is significantly reduced, resulting in energy savings and lower operating costs.
Motor protection is another important aspect addressed by single-phase VFDs. They incorporate various protective features, including overload protection, short circuit detection, and thermal protection, which help safeguard the motor against damage due to excessive current, voltage fluctuations, or overheating. This ensures reliable motor operation, prolongs the motor's lifespan, and reduces the risk of unexpected failures.
Harmonic filtering is also a critical consideration in single-phase VFD applications. When single-phase VFDs operate, they can introduce harmonics into the power supply, which may cause issues such as voltage distortions and interference with other electrical equipment. To mitigate these problems, single-phase VFDs often incorporate harmonic filtering techniques to suppress harmonics and ensure a clean and stable power supply, maintaining power quality and preventing damage to connected equipment.
Control algorithms play a significant role in single-phase VFD operation. These algorithms allow for precise control and adjustment of motor speed, ensuring smooth acceleration, deceleration, and accurate speed regulation. Advanced control algorithms enable efficient motor operation and enhance overall system performance.
In summary, single-phase VFDs provide precise control and regulation of single-phase motors in residential and small-scale applications. With their energy efficiency, motor protection features, harmonic filtering capabilities, and advanced control algorithms, single-phase VFDs enhance motor performance, reduce energy consumption, and ensure reliable operation in various residential and small-scale applications.
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Engineer experience high voltage gate driver bootstrap circuit design
This paper presents a systematic approach for designing high-performance bootstrap gate drivers for power MOSFETs and IGBTs, tailored for high-frequency, high-power, and high-efficiency switching applications. Engineers with varying levels of experience in power electronics can benefit from this comprehensive guide. In most switching applications, the primary factor affecting switching power consumption is the switching speed. Therefore, for the majority of high-power switching applications discussed in this article, optimizing switching characteristics is crucial.
The bootstrap power supply is one of the most commonly used methods to power the high-side gate drive circuits of high-voltage gate driver integrated circuits (ICs). This technique offers advantages such as simplicity and low cost. However, it also comes with certain limitations. First, the duty cycle is constrained by the time required for the bootstrap capacitor to recharge. Second, when the source voltage of the switching device is connected to a negative voltage, significant issues may arise. This article analyzes the most popular bootstrap circuit solutions, including the effects of parasitic parameters, bootstrap resistors, and capacitors on the floating power supply charging process.
2. High-speed Gate Drive Circuit
1. Bootstrap Gate Drive Technology
This section focuses on the requirements of bootstrap gate drive circuits for power MOSFETs and IGBTs in power switching applications with different switching modes. When the input level does not allow direct use of high-type N-channel power MOSFET or IGBT gate driving circuits, we can consider bootstrap gate drive technology. This method is used as the gate drive and bias circuit associated with, where the two are the source of the main switching device as a reference electrode. The driving circuit and the bias circuit in the device with respect to the source voltage swings between two inputs. However, the floating driver circuit and its bias circuit can be implemented by a low pressure, because the input voltage is not applied to these circuits. The drive circuit and the ground control signal are connected through a level shifting circuit. The level shifting circuit must allow for a high voltage difference and a certain capacitive switching current between the floating high side and grounded low side circuits. The high voltage gate drive ICs are separated by a unique level shift design. In order to maintain high efficiency and power consumption can be managed, the level shifter circuit during the main switch is turned on, it can not absorb any current. For this case, we often use a pulsed latch level shifter, as shown in Figure 1.
2. Bootstrap Drive Circuit Works
Bootstrap circuit in the high voltage of the gate driving circuit is useful, as it follows the principle of work. When V_S drops to IC supply voltage V_DD or pulls down to ground (low-side switch turns on, high-side switch turns off), power supply V_DD passes bootstrap resistor, R_BOOT, and bootstrap diode, D_BOOT, bootstrap Capacitor C_BOOT to charge, as shown in Figure 2. When V_S is pulled to a higher voltage on the high side switch, a V_BS of the bootstrap capacitor charging, this time, the floating power supply V_BS, the bootstrap diode is reverse-biased, rail voltage (low-side switch is turned off, high-side switch on) and IC power supply voltage V_DD, is separated away.
3. Shortcomings of Bootstrap Circuit
Bootstrap circuit has the advantage of simplicity and low cost, but it also has some limitations.
And the duty ratio of on-time is limited by the bootstrap capacitor C_BOOT refresh charge required time limit.
The biggest difficulty with this circuit is that when the switching device is turned off, the negative voltage of its source causes the load current to suddenly flow through the freewheeling diode, as shown in Figure 3.
The negative voltage output terminal of the gate driving circuit will cause trouble, because it directly affects the source driving circuit or a PWM control IC pin V_S, may obviously certain internal circuitry down to the ground below in FIG. 4 is shown. Another problem is that the conversion of this negative voltage may cause the bootstrap capacitor to be in an overvoltage condition.
The bootstrap capacitor C_BOOT is instantaneously charged by the power supply VDD through the bootstrap diode D_BOOT.
Since the V_DD supply is referenced to ground, the maximum voltage generated by the bootstrap capacitor is equal to V_DD plus the negative voltage amplitude at the source.
4. V_S Pin Causes a Negative Voltage
As shown in Figure 5, the forward bias of the low-side freewheeling diode is one of the known reasons for lowering V_S below COM (ground).
The main problem occurs during rectification commutation, just before the freewheeling diode begins to clamp.
In this case, the inductors LS1 and LS2 will be down to V_S to the COM, or even more than normal steady state position as described above.
The amplification of this negative voltage is proportional to the parasitic inductance and the turn-off speed of the switching device, di/dt; it is determined by the gate drive resistor, R_GATE and the input capacitance of the switching device, C_iss. The sum of Cgs and Cgd is called Miller capacitance.
Figure 6 depicts the voltage waveform during the turn-off of the high-side N-channel MOSFET.
5. V_S Pin Voltage Undershoot
If the voltage undershoot amplitude exceeds a specified absolute maximum rating, the gate drive integrated circuit is damaged, or the gate drive integrated circuit temporarily latches the current state.
Figure 7 shows a high output signal with the input signal is not changed but the closing lock phenomenon, at this time, the half-bridge circuit external main switch is in the high and low short-circuit state.
If the V_S voltage undershoot does not exceed the specified absolute maximum rating, the gate drive IC will not be damaged. However, when V_S is in the undershoot state as shown in Figure 8, the high-side output does not respond to the input transition. In this case, high-level converter gate driving circuit is not affected by insufficient operating voltage headroom. It should be noted that most of the facts prove that the high-end is usually not necessary to change the state immediately after a switch action.
6. Consider the Blocking Effect
The most complete high voltage gate drive ICs contain parasitic diodes that are broken down in the forward or reverse direction, which can cause parasitic SCR latchup. The end result of the latch-up effect is often unpredictable, ranging from device instability to complete failure. The gate drive integrated circuit may also be indirectly damaged by a series of actions after the initial overvoltage. For example, the latch output leads two simultaneously driven in a high state, causing cross-conduction, causing switch malfunction, and eventually the gate driver integrated circuit catastrophic destruction. If the root cause of the power converter circuit and / or the gate driving integrated circuit by destruction, this failure mode should be considered as a possible. Theoretical limit of the surface may be used to help explain a serious shortage of the voltage V_S and thereby generating the relationship between the locking effect.
In the first case, the use of a "over the bootstrap circuit", V_DD of the circuit is driven by a zero-ohm power supply, a diode is connected to the V_B over through a, as shown in FIG. When a large current flows through the freewheeling diode, since di/dt is large, the V_S voltage will be lower than the ground voltage. At this time, the risk of the latch, because the internal parasitic diode D_BS gate driver, to the final V_S V_B along the direction of conduction, the voltage overshoot caused by the superposition of the V_DD, so that the bootstrap capacitor is overcharged, 10 Shown.
For example: if undershoot V_DD = 15V, V_S exceeds 10V, forcing the floating supply voltage above 25V, the diode D_BS danger of breakdown, thereby generating blocked.
Virtual bootstrap supply is a floating power over Alternatively, as shown in FIG. 11, this time, V_BS is in any case constant. Note that the use of a low-resistance auxiliary supply alternative bootstrap circuit can achieve this. In this case the maximum power V_BS, if the overshoot exceeds V_S data table (Datasheet) a predetermined pressure, the risk lockout occurs because the parasitic diode D_BCM COM final end along the direction V_B is turned on, as shown in Fig.
A practical circuit may be in between these two limits, the result is V_BS voltage slightly increases, slightly lower than, V_B, as shown in Fig.
To be precise, any extreme situation is prevalent, as tested below. If V_S overshoot duration more than 10 ns, is overcharged bootstrap capacitor C_BOOT, then the high side gate driver circuit over-voltage stress destruction, as the V_BS voltage exceeds the data table specified absolute maximum voltage (V_BSMAX). When designing a bootstrap circuit, its output voltage must not exceed the absolute maximum voltage rating of the high-side gate driver.
7. Parasitic Inductance Effect
The amplitude of the negative voltage is:
In order to reduce the slope of the current flowing through the parasitic inductance as a function of time, the derivative term in Equation 1 is minimized.
For example: a 10 amps, 25V gate drive, which is parasitic inductance 100nH, if the switch within 50ns, then a negative voltage spikes between V_S and ground is 20V.
3. Design Process of Bootstrap Parts
Select a bootstrap capacitor
The bootstrap capacitor (C_BOOT) is charged each time the low-side driver turns on and the output voltage is lower than the gate driver supply voltage (V_DD). The bootstrap capacitor is only discharged when the high side switch is turned on. The bootstrap capacitor supplies power to the high-end circuitry (V_BS). The first parameter to consider is the maximum voltage drop of the bootstrap capacitor when the high-side switch is on. The maximum allowable voltage drop (V_BOOT) depends on the minimum gate drive voltage to be maintained (for high-side switch). If V_GSMIN is the minimum gate-to-source voltage, the voltage drop across the capacitor must be:
among them:
V_DD = the supply voltage of the gate driver;
V_F = bootstrap diode forward voltage drop [V]
Calculate the bootstrap capacitor as:
Where Q_TOTAL is the total amount of charge in the capacitor. The total charge of the bootstrap capacitor is calculated by Equation 4:
among them:
Q_GATE = total amount of gate charge
I_LKGS = switching gate-source level leakage current;
I_LKCAP = leakage current of the bootstrap capacitor;
I_QBS = quiescent current of the bootstrap circuit;
I_LK = leakage current of the bootstrap circuit;
Q_LS = charge required by the internal level shifter for all high voltage gates
Polar drive circuit, the value is 3nC;
t_ON = high end on time; and
I_LKDIODED = leakage current of the bootstrap diode;
The leakage current of the capacitor, and only in the use of electrolytic capacitors, it needs to be considered, otherwise, can be ignored.
2. Choose Bootstrap Resistance
When using an external bootstrap resistor, the resistor R_BOOT brings an extra voltage drop:
among them:
I_CHARGE = charging current of the bootstrap capacitor;
R_BOOT = bootstrap resistance; and
t_CHARGE = charging time of the bootstrap capacitor (low-side conduction time)
The resistance value (typically 5 ~ 10 Ω) can not be too large, otherwise it will increase the time constant of V_BS. When calculating the maximum allowable voltage drop (V_BOOT), must be considered bootstrap diode voltage drop. If the voltage drop is too large or the circuit can not provide a sufficient charging time, we can use a fast or ultra-fast recovery diode recovery.
For example, when using an external bootstrap diode, estimate the size of the bootstrap capacitor.
Gate drive IC=FAN7382
Switching device=FCP20N60
Bootstrap diode=UF4007
V_DD=15V
Q_GATE=98nC (maximum)
I_LKGS=100nA (maximum)
I_LKCAP=0 (ceramic capacitor)
I_QBS=120A (maximum)
I_LK=50A (maximum)
Q_LS=3nC
T_ON=25s (f_s=20KHz, duty cycle = 50%)
I_LKDIODE=10nA
If the bootstrap capacitor is on when the high side switch is on, the maximum allowable voltage drop is 1.0V and the minimum capacitance value is calculated by Equation 3.
The bootstrap capacitor is calculated as follows:
The voltage drop caused by the external diode is approximately 0.7V. Assuming that the capacitor charge time is equal to high on-time (duty ratio of 50%). According to different bootstrap capacitor values, use the following equation:
The recommended capacitor values are 100nF ~ 570nF, but the actual capacitor value must be chosen based on the device used. If the capacitance value is too large, the charging time of the bootstrap capacitor is reduced, and the low-side conduction time may not be sufficient to make the capacitor reach the bootstrap voltage.
4. Consider the Bootstrap Application Circuit
1. Bootstrap Start Circuit
As shown in Figure 1, the bootstrap circuit is useful for high voltage gate drivers. However, when the source of the main MOSFET (Q1) and the negative bias node of the bootstrap capacitor (C_BOOT) are at the output voltage, it has the problem of initializing and charging the bootstrap capacitor. At startup, the bootstrap diode (D_BOOT) may be reverse biased, the main MOSFET (Q1) has insufficient turn-on time, and the bootstrap capacitor cannot hold the required charge, as shown in Figure 1.
In some applications, such as battery chargers, the output voltage may already exist before the input power is loaded into the converter. It may not be possible to provide an initial charge to the bootstrap capacitor (C_BOOT), depending on the voltage difference between the supply voltage (V_DD) and the output voltage (V_OUT). Assuming that there is enough voltage difference between the input voltage (V_DC) and the output voltage (V_OUT), the circuit consisting of the start-up resistor (R_START), the start-up diode (D_START) and the Zener diode (D_START) can solve This problem is shown in Figure 14. In this startup circuit, the startup diode D_START acts as a secondary bootstrap diode that charges the bootstrap capacitor (C_BOOT) on power-up. After the bootstrap capacitor (C_BOOT) is charged, it is connected to the Zener diode D_Z. In normal operation, this voltage should be greater than the driver's supply voltage (V_DD). The startup resistor limits the charge current and Zener current of the bootstrap capacitor. For maximum efficiency, the proper starting resistor value should be chosen so that the current is extremely low because the bootstrap path through the startup diode in the circuit is constant.
2. Bootstrap Diode Series Resistor
In the first option, the bootstrap circuit includes a small resistor, R_BOOT, which is connected in series with a bootstrap diode, as shown in Figure 15. The bootstrap resistor R_BOOT is used to limit current only during the bootstrap charge cycle. The bootstrap charge cycle indicates that V_S falls below the integrated circuit supply voltage V_DD, or V_S is pulled low to ground (the low side switch turns on and the high side switch turns off). The power supply V_DD charges the bootstrap capacitor C_BOOT through the bootstrap resistor R_BOOT and the diode D_BOOT. The breakdown voltage (BV) of the bootstrap diode must be greater than V_DC and the recovery time is fast enough to reduce the charge that the bootstrap capacitor feeds back to the power supply V_CC.
This is a simple way to limit the initial charge current of the bootstrap capacitor, but it also has some drawbacks. Duty cycle is limited by the time the bootstrap capacitor C_BOOT refresh charge required, and startup problems. The resistance value (generally 5~10 Ω) should not be too large, otherwise the V_BS time constant will increase. The minimum on-time, the time to charge or refresh the charge to the bootstrap capacitor, must match this time constant. This time constant depends on the bootstrap resistor, the duty ratio of the bootstrap capacitor and the switching device is calculated by the following equation:
Wherein R_BOOT bootstrap resistor; C_BOOT is the bootstrap capacitor; D is the duty ratio.
For example, R_BOOT = 10, C_BOOT = 1F and D = 10%; the time constant is calculated as follows:
Even if a reasonably large connecting the bootstrap capacitor and a resistor, the time constant may be increased. This method can alleviate this problem. Unfortunately, the series resistance can not solve the problem of over-voltage, and slowing the bootstrap capacitor recharging process.
3. VS and VOUT Resistance
In the second option, add a small resistor RVS between V_S and V_OUT of the bootstrap circuit, as shown in Figure 16. The recommended value for R_VS is around a few ohms.
R_VS not only as a bootstrap resistor also serves as the on-resistance and the off resistance, as shown in Figure 17. The bootstrap resistance, on-resistance, and turn-off resistance are calculated by the following equation:
4. V_S Clamp Diode and Rearranged Gate Resistor
In the third option, the bootstrap circuit rearranges the gate resistor between V_S and V_OUT and adds a low forward voltage drop Schottky diode between V_S and ground, as shown in Figure 18. Show. The voltage difference between V_B and V_S, should be maintained within a predetermined range of the absolute maximum ratings of the data table, and must conform to the following equation:
5. Reset Gate Resistance; Dual Purpose
The gate resistor sets the turn-on and turn-off speeds of the MOSFET, limiting the current of the Schottky diode when the voltage at the source of the main switch is negative. In addition, the dual diodes connected to the ends of C_BOOT ensure that the bootstrap capacitor does not overvoltage. The only potential danger of this circuit is that the charge current of the bootstrap capacitor must flow through the gate resistor. The time constants of C_BOOT and R_GATE slow down the capacitor recharge process, which may be a limiting factor similar to the PWM duty cycle.
The fourth choice, comprised between V_S and V_OUT, rearranging a gate resistor, and V_S is placed between a clamp and the pressure device 19, a zener diode is arranged and 600V diode. Quantify the Zener voltage according to the following rules:
5. Select HVIC Current Capability
For each rated drive current, calculate the maximum gate charge Q_G that can be switched within a specified time, as shown in Table 1.
Description:
1. A single channel 4A HVIC, equivalent to a dual channel 2A HVIC!
For example, the switching time of 100ns is:
At 100KHz, 1% of the switching circuit switching period;
At 300KHz, the conversion circuit switching cycle is 3%;
1. The required nominal gate drive current depends on the number of gate charges Q_G that must be moved during the switching time t_SW_ON/OFF (because the average gate current during switching is I_G):
2. Maximum gate charge Q_G, obtained from the MOSFET datasheet.
If the actual gate drive voltage V_GS of the specification table the different test conditions, we can replace the value of Q_G V_GS curve used. Multiplying the value in the datasheet by the number of MOSFETs connected in parallel is the desired value.
3. t_SW_ON/OFF indicates the required MOSFET switching speed. If the value is unknown, take 2% of the switching period t_SW:
If the channel (VI) switching loss is dominated by switching (on or off), the driver needs to be adjusted according to the conversion. For clamped inductive switches (normal), the channel switching losses for each conversion are estimated as follows:
among them
V_DS and I_D are the maximum values for each switching interval.
4. The approximate current drive capability of the gate driver is calculated as follows
(1) Current capability (conduction)
(2) Current sinking capacity (shutdown)
among them:
Q_G = V_GS = V_DD, the gate charge of the MOSFET;
t_SW_ON/OFF = MOSFET switch on/off time; and
Experience factor = 1.5 (by delay and parasitics impact by the driver corresponding to the input stage)
6. Gate Resistance Design Flow
The switching speed of the output transistors is controlled by the turn-on and turn-off gate resistors that control the turn-on and turn-off currents of the gate drivers. This section describes the basic rules for gate resistance by introducing the equivalent output resistance of the gate driver to achieve the desired switching time and speed. FIG 20 describes an equivalent circuit of the gate driver, and a current flow path is turned on and off during which includes a gate driver and a switching device.
Figure 21 shows the gate of the switching device during turn-on and turn-off - charge-transporting properties.
Quantize the on-resistance
The switching time t_sw, selecting turn-on gate resistor R_g (ON), the switching time to obtain the desired. The resistance values are determined when the switching time, we need to know the power supply voltage V_DD (or V_BS), the gate driver equivalent on-resistance (R_DRV (ON)) parameter, and the switching device (Q_gs, Q_gd, and V_gs(th)).
The switching time is defined as the time it takes to reach the end of the platform voltage (which provides a total of Q_gd + Q_gd to the MOSFET), as shown in Figure 21. The turn-on gate resistance is calculated as follows:
Where R_g(ON) is the gate on-resistance and R_DRV(ON) is the equivalent on-resistance of the driver.
Output Voltage Slope
The turn-on gate resistance R_g(ON) is determined by controlling the output voltage slope (dV_OUT/dt). When the output voltage is non-linear, the slope of the maximum output voltage can be approximated as:
Insert the deformation expression I_g(avr) and sort it out:
Where C_gd(off) is the Miller effect capacitor and is defined as C_rss in the datasheet.
Quantify Turn-off Gate Resistance
In quantifying the turn-off resistance, the worst case is when the MOSFET drain is off, an external action forces the resistor to rectify.
In this case, dv / dt output node, inducing an electric current through the parasitic through C_gd, flow R_G (OFF) and R_DRV (OFF), shown in Figure 22.
Set forth below, when the output dv / dt turned on when accompanied by its cause, how to quantify the off resistance MSOFET, 22 shown in FIG.
For this reason, the impedance must be turned off according to the amount of the worst applications. The following equation correlates the MOSFET gate threshold voltage with the drain dv/dt:
Design Examples
Use Fairchild's MOSFET FCP20N60 and gate driver FAN7382 to determine the turn-on and turn-off gate resistance. The parameters of the FCP20N60 power MOSFET are as follows:
Q_gs = 13.5nC, Q_gd =36nC, C_gd =95pF, V_GS(th) =5V, V_GS(th)MIN =3V
4.1 Turn-on Gate Resistance
1) If V_DD=15V, the required switching time is 500ns, calculate the average gate charging current:
The on-resistance value is approximately 58 Ω.
2) If VDD=15V, dVout/dt=1V/ns, the total gate resistance is calculated as:
The on-resistance value is approximately 62 Ω.
4.2 Turn off the Gate Resistance
If dV_out/dt = 1V/ns, the turn-off gate resistance can be calculated as:
7. Consider Power Consumption
1. Gate Driver Power Consumption
The total power consumption includes gate driver power and bootstrap diode power. The gate driver power consumption consists of static power and dynamic power. It is related to the switching frequency, high and low output load capacitance of the driver, and a power supply V_DD.
Static power consumption because the power supply V_DD to the low side driver of the quiescent current, leakage current and high-level conversion stage drive caused. The former depends on the voltage at the V_S terminal, which is proportional to the duty cycle only when the high-side power device is turned on.
Dynamic power is defined as follows: For low-end drivers, there are two different sources of dynamic power. First, when the load capacitor is charged or discharged through the gate resistor, half of the energy entering the capacitor is dissipated on the resistor. Power consumption of the gate drive resistor, the inside and outside of the gate driver, and the switching power CMOS internal circuit. At the same time, the dynamic power consumption of high-end drivers also includes two different sources. One is because of the level shifting circuit, and the other is because of the charging and discharging of the high-side capacitor. Here, static power consumption can be ignored because the total power consumption of the integrated circuit is mainly the dynamic power consumption of the gate drive IC, which can be estimated as:
Figure 23 shows the estimated gate driver power dissipation for different frequencies and load capacitances when V_DD=15V. This curve can be used to approximate the power consumption of the gate driver.