Abstract: This article is an implementation scheme of a multi-chip digital signal processing system based on ADSP-TS101S. The system is applied to the signal processor of a certain radar. The article first introduces the composition of the signal processing system composed of multiple TIgerSHARC DSP chips; secondly, estimates the amount of calculation of the system and the required calculation time; finally, it specifically explains how the CPLD generates the reset signal and realizes the parallel-serial conversion function. Introduction With the continuous improvement of people's requirements for real-time signal processing and the rapid development of large-scale integrated circuits, DSP, which is the core and symbol of digital signal processing, has been rapidly developed and applied. This text is based on a DSP of ADI Company-TIgerSHARC, introduces a set of concrete realization scheme in the signal processing system in more detail. Figure 1 Block diagram of the signal processor System design and function introduction of each part This system is a signal processor of a certain radar. It reads intermediate frequency data through ADC. DSP1 and DSP2 complete the pulse compression and sidelobe suppression of the data. DSP3 and DSP4 complete the data accumulation and modeling, and DSP5 implements it. Normalize video data, output video data through DAC, and send parallel data. The system structure is shown in Figure 1. Figure 2 Block diagram of pulse compression filter algorithm Figure 3 Power-on reset waveform of TigerSHARC DSP System calculation analysis and calculation time estimation According to the task of signal radar processing, the calculation amount of each component of the system is specifically analyzed below to estimate the required calculation time. (Signal processing should be less than 1ms per frame) CPLD generates reset signal and realizes parallel-serial conversion function Reset signal generation Conclusion The implementation of the multi-chip TigerSHARC DSP in the real-time signal processing system introduced in this article has been successfully applied to the improvement of the signal processor of a certain radar. In terms of structure, the original three circuit boards are merged into one; the number of chips has been reduced from the original (ADSP21062) dozens to five (ADSP TS101S). On the basis of completing the original functions, some functions to improve performance have also been realized. And the power consumption of the new system is greatly reduced compared with the original, and the heat dissipation is also significantly reduced. Practice shows that the hardware structure of the system composed of TigerSHARC DSP is simple, the software is easy to write, and the cost is low, and it has high engineering application value. Magnetic Transducer External Drive Type
The magnetic transducers (External Drive Type) are
versatile and customizable to different physical sizes, housings, mounting
options, power consumptions. Our magnetic transducers are engineered to be used
with an external drive circuit. This allows our customers the flexibility to
design and customize the circuitry to meet their needs. External circuitry
allows different frequency ranges to be used to create multiple sounds through
excitation waveform. Our magnetic transducers come in a slim-line profile and
are a cost-effective solution. Our extensive capabilities make our magnetic transducers
an excellent solution for high/low tones, siren, and chime sounds.
Piezoelectric Buzzer,Passive Magnetic Buzzer,External Drive Buzzer,Magnetic Transducer External Drive Type Jiangsu Huawha Electronices Co.,Ltd , https://www.hnbuzzer.com
In this system, ADC adopts AD9225 with 12 effective data bits and 25MSPS conversion rate to convert I and Q analog signals into digital signals at a certain sampling rate, and the high 10 bits are sent to DSP.
This system uses TIgerSHARC DSP, the chip has a maximum operating speed of 300MHz, a core instruction cycle of 3.3ns, and can execute up to 4 instructions per cycle, 24 16-bit fixed-point operations and 6 floating-point operations, and contains 6MB of on-chip SRAM , With high storage and computing performance, high application value in the field of signal processing. In order to simplify the system hardware and reduce the connection between DSP slices, the 5 DSPs of the system are connected in a loosely coupled link. DSP1 reads the I and Q data after IF demodulation through external DMA, DSP1 performs pulse compression (matched filtering) on ​​part of the read data, and sends the processed data and unprocessed data to link port 2 DSP2. DSP2 performs pulse compression on the remaining data. DSP2 sends all processed data to DSP3. Due to the accumulation of dozens of frames and the large amount of data, DSP3 and DSP4 respectively undertake half of the data accumulation and modulo calculation. DSP4 sends the modulus result to DSP5. DSP5 normalizes the data to generate video data, and the video data is sent out through an external port in a DMA mode. Also send parallel data to CPLD in different working modes.
Program loading: This system adopts EPROM program boot mode. When using the link port of TIgerSHARC DSP for data transmission, the word length must be set to 4 words each time, the number of words sent must be a multiple of 4, and the data start address must be aligned every 4 words. So the sender DSP must read 4 32-bit words from EPROM every time and send them through the load link.
DAC adopts high-speed device AD9750 with 10 effective data bits and 125MSPS conversion rate to convert video data into analog signal at a certain fixed rate. 
CPLD completes functions such as data latching, DSP reset signal generation, and conversion of parallel data to serial data output at a certain baud rate (serial output meets the RS-232 standard).
Clock: DSP uses the clock generated by the on-board 40MHz crystal oscillator. The A/D sampling clock should be phase-locked with the system clock, so the 10MHz system clock is phase-locked to 40MHz by the ICS 601M, and then input to the CPLD via pin 40ME. After frequency division, the A/D sampling clock signal is generated, and the working clock for D/A sampling is also Produced by it. When debugging a single board, only the internal clock can be used, so the 40ME must be selected with a jumper.
Power supply: TigerSHARC DSP has three power supplies, digital 3.3V, used for I/O power supply; digital 1.2V, used for DSP core power supply; analog 1.2V, used for internal phase-locked loop and frequency multiplier circuit power supply. TigerSHARC DSP requires that the digital 3.3V and 1.2V should be powered on at the same time. If strict synchronization is not possible, ensure that the 1.2V core power supply is powered on first, and the I/O power supply is powered on after 3.3V. In this system, a large capacitor is connected to the digital 3.3V input terminal, and a small capacitor is connected to the digital 1.2V input terminal, so that the 3.3V charging time is longer than the 1.2V charging time, which solves the problem of power supply sequence. The digital 1.2 V power supply of each DSP is supplied by a MAX1951 which converts +5V into 1.2V. The analog 1.2V power supply of all DSPs is uniformly supplied by a piece of REG1117A which converts the analog +5V into 1.2V. The I/O 3.3V power supply of 5 pieces of DSP is supplied uniformly by a piece of REG1117 which converts the digital +5V into 3.3V.
Pulse compression FFT technology is used to achieve pulse compression filtering, and the algorithm is shown in Figure 2. According to the calculation needs, 512, 1024 and 4096 point complex FFTs are required. After the complex FFT is completed, it must be multiplied by the pre-stored matched filter coefficient H(k), which requires 512, 1024, and 4096 complex multiplications, and the multiplication result also requires 512, 1024, and 4096-point complex IFFT to obtain Pulse pressure results. It takes about 50ms (working at 200MHz) for TS101 to do 1024-point complex FFT (IFFT) in the actual application of this system. It can take full advantage of the TS101 dual arithmetic block, single instruction multiple data (SIMD) features, and perform complex multiplication of two distance units at the same time. It only takes 15ms to complete 1024 complex multiplications. It takes 60ms, 120ms and 460ms to complete the pulse compression of 512, 1024 and 4096 points in this way. Because DSP1 must adopt DMA way to read each frame data segmentation, there is not enough time to carry on 4096-point pulse compression, so put it in DSP2 to finish.
Sidelobe suppression The time domain synthesis method is used to suppress the sidelobe of the two-phase code, and the sidelobe suppression coefficient is integrated in the matched filter coefficient of the pulse compression, so as to achieve the effect of suppressing the sidelobe. The algorithm is implemented on the basis of pulse compression, and has no additional impact on the amount of calculation and time of the DSP.
Accumulation Accumulation adopts the sliding window accumulation method, which requires less calculation, and TS101 has a large time surplus. Actually, it requires at least 35 frames to accumulate. Each cycle I and Q have a total of 2×3200 points, which requires about 2×3200×35=224K bytes of storage space. Therefore, the accumulation calculation is completed in DSP3 and DSP4 respectively.
The power-on reset type of TigerSHARC DSP is relatively special, and should be paid attention to when designing. This system uses Altera's CPLD EPM7192 to generate power-on reset waveforms and timing control. The power-on reset waveform requirements are shown in Figure 3.
It should be noted here:
tstart_LO must be greater than 1ms after the power supply is stable;
tpulse1_HI must be greater than 50 system clock cycles and less than 100 system clock cycles;
tpulse2_LO must be greater than 100 system clock cycles.
Normal reset after DSP is powered on: the low level duration must be greater than 100 system clock cycles.
The realization of parallel-serial conversion function Parallel data is sent to CPLD by DSP, and it is converted into serial data through CPLD and sent at a certain fixed baud rate. The program written in the AHDL language supported by MAX+plusII has been tested to realize the parallel-to-serial conversion function, which has the advantages of flexibility, simplicity and strong scalability. The specific procedures will not be repeated.